1. Field of the Invention
The present invention relates to devices which order cycled data in pipeline data systems, and, more particularly to devices which order cycled data in PC's having data pipeline capacity.
2. Description of the Related Art
Many personal computer systems developed in the past have included a central processing unit (CPU) which issues commands to other system components (e.g., memory storage devices, input/output units, etc.) and processes data received from these components. Typically, the CPU issues a single command, or request, to one of the system components, for example, the memory, and waits for the component to respond to this command. Once the memory has issued a response, the CPU is free to issue another command which may go to the same component or to another system component. Thus, in these systems, only a single command is pending at any one time so that the CPU must wait while the designated system component generates a response to the issued command.
In an effort to increase the efficiency and processing capacity of personal computers, a new generation of data pipelining computers, such as the Intel.RTM.PENTIUM processor, has been developed. Data pipelining systems allow more than one request to be transmitted at a time so that at any given time two or more command requests may be pending. Personal computer systems that include such pipelining capability are able to issue a first command and subsequently issue a second command before receiving a response to the first command.
One problem associated with data pipelining in personal computers is the managing of data requests and responses. For example, if the CPU issues a first command to a relatively slow memory unit and the CPU then issues a second command to a faster memory unit before a response is received from the first memory unit, then it is possible that the second, faster memory unit will issue a response before the first memory unit issues a response. The CPU will therefore receive the responses in a reverse order so that the second response will be given to the first command, while the first response will be given to the second command.
Therefore, a need exists for a data management system which orders the issuance of data responses so that the correct responses are always given to the corresponding CPU commands.